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COGRE: A Novel Compact Logic Cell Architecture for Area Minimization
Masahiro IIDA Motoki AMAGASAKI Yasuhiro OKAMOTO Qian ZHAO Toshinori SUEYOSHI
Publication
IEICE TRANSACTIONS on Information and Systems
Vol.E95D
No.2
pp.294302 Publication Date: 2012/02/01 Online ISSN: 17451361
DOI: 10.1587/transinf.E95.D.294 Print ISSN: 09168532 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Architecture Keyword: reconfigurable logic, COGRE, NPNequivalent classes,
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Summary:
Because of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a smallmemory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPNequivalence class. The results of our investigation show that only small portions of the NPNequivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPNequivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4COGRE is smaller than that of 4LUT and 5LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8COGRE is 75.19% less than that of 8LUT. Further, the total number of configuration memory bits of 4COGRE is 8.26% less than the number of configuration memory bits of 4LUT. The total number of configuration memory bits of 8COGRE is 68.27% less than the number of configuration memory bits of 8LUT.

